Modulus of the Counter & Counting up to Particular Value Neso Academy

Digital Electronics: Modulus of the Counter & Counting up to Particular Value

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1. forsaken: sir,i am not getting clarity if i tried to understand how to count down to a particular value
2. rishav mahajan: Sir how to design mod-5 counter
3. akash singh: please tell me how to construct mod-10 counter using mod-2 and mod-5 counter.Moreover the gates which u have given will se same in all the cases???
4. Ritesh Sahare: I need a solution for mod-6 counter using jk flip flop I'm not getting the truth table
5. Manoj Maharaj: abhinaw kumar To bring Qa Qb Qc values back to 0 0 0 because after 6 it should go back to 0 and start counting from 1 to 6 again since its a mod 6 counter..But there are 8 values here so after 6th values we reset it back 0 using NAND
6. Other Guy: Fab❤
7. viraj sadhale: In the state diagram of counters with unused states, the unused states can be added to any valid state, or there must be some reason to add it?
8. Trai: You are the best teacher on this subject that I found on THE INTERNET. Very clear and easy to understand. Thank you.
9. sanjay mouli: Please! Make a video atleast 2 examples of MOD counter!
10. Kushwanth Kapa: why can't u use in nand gate of inputs only QB and QC
11. Affan Hassan: what is a modulo-59 counter?
12. Venkatesa Srikanth: please construct mod 6 counter
13. Saumya Gupta: don't u think that if u connect youre preset to logic 1 the preset input to the ff will become 0 and then the set action will be happening
14. SHUBHAM YADAV: Sir please tell me how to design ripple counter count from 3 to 13
15. Akshay Menon: Hello! Could you please upload  lectures on Registers? Thank you!
16. ARKA PRAMANIK: whenver for the clr qa ,qb,qc became 0 then we get 000 but then the clr has became 1 also for qa ,qb,qc 0 in nand gate and you have also make the preset 0 and you have claimed in previous presentation that prst1 and clr1 is not allowed??
17. Nehal Chavan: sir the question which u gave to solve about conversion of 1ff to another ff,for first one i.e T ff to SR ff i have got T as Qn'S+QnR,and for second one i.e JK ff to SR ff i got J=S,k=S'R.whether calculated results are correct!if no reply sir.
18. Swapnil Dudhane: +GOLAKOTI VEERA VENKATA SATYANARAYANA MAYBE you should probably reset the states 0,1,2,3 and you will require a 4 bit counter. Not Sure though
19. Anantha Lakshmi Battula: thanku so much:)
20. ProgrammerDost: what will happen if i set PST or CLR to 1.
21. Swarnava Bannerjee: Excellent explanation.
22. AdityaFingerstyle: No! It should be 110(6). If you used 101(5) then 5 won't be counted. What we really want is count up to 5 and then when 6 arrives reset the counter to 0.
23. Shah Rahul: +Meghna SIngh ty meghna ..and u can do it
24. Nehal Chavan: hello sir,it had been very interesting to watch your lecture , the way you explained all sections of digital techniques .i have gone through your videos and i have understood all concepts which you presented.thank you for being guideline .
25. Atharva bais: Sir in the description please upload the contents of the board as pdf so that we can use them as notes.
26. vikas jaiswal: sir,how to get MOD -7 counter
27. Aevai_212: Hi sir ... upload videos for synch counters mod 12 please
28. tech info computer: A one sir.....
29. kamlesh kunwar: I think ..this tutorial has a bug ... in the NAND gate u should take 101(5) as a input..u took 110(6) as input ..Do a recheck once ..!!
30. zarkbark: T flip flops would work the same, correct?
31. Nikhil Gadkari: how can i design 9 mod counter using t flip flop please help..!
32. Nithya Srinivasan: in mod 6 counter will 6 be displayed in d output?? bcoz since d output of d flipflop in connected to the input of nand gate output will be displayed and later the flip-flops will be cleared... plz clarify this.. really confusing... But have to tell u ur approach to teaching d concepts is fantastic...
33. Meghna SIngh: Whenever it hits 110, counter is going to be RESET, so 111 state never achieved and it starts back from 000.
34. Abhishek verma: now these words are really small for such quality lectures that u provides us for free, but again thank u sir...thank u for being here
35. SUNDERAM SAH 15BEC0004: use more examples and how to do for synchronous
36. upasana Roy Chowdhury: Best academy
37. Sanjay Goyal: you are god of digital
38. Aditya Jaiswal: really best digital electronics lecture for BTECH students in whole youtube
39. Heitler Remlalfaka: also sir, i have simulated the ckt on http://www.falstad.com/circuit/e-counter.html i think instead of NAND for teh reset the op of NAND should be OR again with 0 then given to all RESETs.. then only teh ckt will work as desired. correct me if i am wrong. Bcoz, the circuit above will produce RESET=1 => Q=0 FROM THE FORST CLOCK signal itself
40. Neso Academy: +vaibhav chauhan It means you want MOD-5 counter. And in that case as soon as 5th state arrives you have to reset all the flip flop so that output of your counter is '000'. Don't reset it when 4th state arrives, because you want to count 4 completely. 5th state is 101 so input to the NAND gate is QC,QB' & QA.
41. Prince Thushara: god bless u man
42. Sai kumar Naik: sir your teaching videos are like RED BULL DRINK to who(to engineering students ) is walking in a desert(engineering collages without good DD teacher)... good job sir .A VERY SPECIAL THANKS FROM NIT MANIPUR STUDENT.
43. Jamal Virani: found this channel just in time for my exam, you are a life saver
44. Shikhar Jaiswal: circuit diagram using t - flip flopof mod 11 asnchronous up counter how to implement this sir
45. Vrushabh: Sir u r like a god for us... Love u and gbu sir
46. gursharan singh: what will happen when clr becomes 1
47. Jalaluddin Khan: sir make one lecture on find "K" in MOD - K counter.
48. abhinaw kumar: for clr why you used NAND gate ?please explain soon.....
49. vikram Dubey: easy to understand now...
50. Shahid Nawaz Khan: don't we have to clear when output is five? because then the next time it will be zero, if we do this for six, six will be the last output
51. Amogha Subramanya D A: Since, the clear input is active low, we have to use NAND gate for 7476 JK Flip-flop IC to Reset.
52. Mya Ortega: Hi, can you do a tutorial on this using an IC? i.e, 74LS293. It would be appreciated! Thanks!
53. Adham nabulsi Fans: hello can you do the counters asynchnous modulus 10,15,20 ..? please do it , I have an examen but I not inderstand  this modulus
54. Oju Shikhare: saved my semester <3
55. ABHISHEK KUMAR: How to Design a MOD 5 , 4-Bit synchronous counter to count in perticular sequence
56. Kirk Hammer 2010: I disagree, i think we should trigger CLEAR when '5' appears , becoz Qc ,Qb, Qa, already show 101 before triggering CLR, , after '5' they trigger CLR and display '0'. Plz convince me how '6' is "Not displayed" when Qc ,Qb, Qa, = 110 after then they trigger CLR, , (in your ckt 12:30 onwards , i think '0' appears at 7th clk edge and 110 = 6 appears at 6th clk edge )
57. A Leponzo: So, the same clearing and presetting idea can be used for counting down to a particular value also?
58. Akash Malhotra: +Trai I agree. Nesa Academy is awesome!
59. forsaken: to clr
60. Apostolos Mavropoulos: dear sir please explain, if we dont have negative logic for PST & CLR (so the PST=1 -> Q=1 & CLR =1 -> Q=0) inputs, are we supposed to use nor gate instead of nand fore reset condition?
61. Taurus Chinni: honestly....Ur teaching was fabulous😃😊
62. Heitler Remlalfaka: sir, questn, does the NAND gate logic work for all counters that count to a specific value, in this case we caount to dec5 and after that it restarts from 0 and the NAND gate helps did that, what if we want to count to 7 and reset after that, will the NAND logic still work in that case?
63. Salman Khan: +Kodipalli Vaishnavi you may use NOR gate but i think if we will always use NAND gate then it will reduce confusion
64. AKASH DIXIT: Hey can u tell about BCD counter ..which modulus it is & how it works
65. Shafqat Jamal: Very good explanation
66. How come: if the flip flops were positive going edges, what changes will happen??
67. BHASKAR RAO P: I too think that when 101 is countered immideately clear should be triggered
68. B. M. Rakibul Hasan: is it the same as up or down counter.here in up counter mod 6 unter using mod 8.you add nand gate.if it is in down counter mod 6 using mod 8 .what gate use
69. Anantha Lakshmi Battula: thanku so much:)
70. forsaken: to clr
71. Neeraj Negi: the best resource on the internet!
72. Revanth Raj: Hello Sir, please upload videos for synchronous counters
73. hussein gharakhani: Thank you so much. You ARE GREAT!
74. Gurveer Kaur: Concept cleared👍🏻 tysm !
75. Hassan Alshehri: In this example, the requirement for the counter is to count up to 5 (101), however, the combinational circuit for the clear input allows the counter to count up to 6 (110). I'm thinking that the combinational circuit for the clear input should be (Q_A Q_B' Q_C)'. That is once the counter reaches 101, the counter should start counting from 000. Please let me know if i missed something. Thnaks!
76. Arshdeep Singh: Where to connect the inputs of NAND gate, Kindly Explain ?
77. Raja Haseeb: i think we have to skip these state but i dont know how
78. blue sky: life saver
79. rachid guernouti: can we use a decoder instead of the NAND gate to restart our counting
80. Joshua Perez: How do you count from a certain value ex: 2 to 8
81. sonia grover: Why u use only nand gate why not any other??
82. GOLAKOTI VEERA VENKATA SATYANARAYANA: I Understood these concepts very clearly. I Have small doubt " How to design a Counter if they have given sequence like 4,5,6,7,8,9?"
83. Arunava Basak: +nikhil gadkari make a 4 bit I,e. mod 16 counter and add the same nand gate to the clrs of gates with the gate(4 input nand) having Qd, Qc', Qb, Qa' (1010 -> dec 10)connected
84. Ayushi Tomar: Thank u very much sir.It helped me alot
85. Brian Nguyen: Yes
86. Mike Rousi: "I hope you have watched my presentantion" Me:"Fine ill look it up." Video i look up:"I hope you have watched my presentation on...." Me:"Okay,ill look that up" Next Video:"I hope you have watched my presentati-" Me:"..." Your videos are awesome tho,reminding us to check the presentantion helps to understand everything without missing something important and to put things in a correct order.
87. Snehal Javheri: How can we design logic for Reset by using K map ?
88. Terrence Jones: You are king!
89. aashish sahu: sir could you please tell me can we use AND Gate instead of NAND Gate. if NO then why?????
90. Speakingwords India: Please explain the generation of spikes or glitch
91. Raja Saad: fabulous!! appreciate ur effort...
92. Nikhil Gadkari: +Arunava Basak thanks a lot it helped😊
93. Neso Academy: +Raja Saad Thank you!
94. Debdeep Das: is set and reset are preset and clear respectively in some ics?
95. loga rathinam: You are enough for me to complete this course successfully...
96. ProgrammerDost: Sir The way you teach is awesome. thank you
97. Prasang Singhal: Fabulous..... Can I use 2 input nand gate and set its input as Qc and Qb...??
98. Neso Academy: +ajay arya most welcome! comment like this keeps me going. I will complete the course soon.
99. Kshitij Vengurlekar: Thanks :)
100. Govardhan Reddy: also nand gates dont have delays hence when 6 comes immediately it resets to 0.
101. Sujoy Roy: What if we have to start our count from a particular value say 2 (010)?
102. Niraj Kumar: The way u taught is really commendable!!!!!!!!!!!!!!!!!!!!!!!!!
103. Yash Agarwal: Thanks a tone sir ...☺☺
104. Neso Academy: +Hassan Alshehri If you do that it will not count 5 but 4. Because as soon as 5th pulse comes your logic will reset it. We want to have 5 completely so we reset it when 6 comes. In this way we have the complete 5th pulse.
105. Gobiga Rajalingam: Are there any videos on counting down to a truncated mod value ? I've tried looking for it,but couldn't find any.Any help would be welcome...
106. Arsalan Azeem: how to count let us say from 3 to 6
107. Mrunank Mistry: thnx brooooooo!!!!!!!!!!!
108. Julia Dungu: How can i count starting from a specific value (for example from 2 to 8)?
109. Kshitij Upadhyay: sir is preset same as reset and clr same as set
110. Uday Charan: What about MOD-9
111. Fatih Koç: which is the differences between the reset and modulus counter?
112. vaibhav chauhan: Bro what to do if we want upto 4th state ?
113. Qiyuan Wu: So is this modulo 6 counter synchronous?
114. Shubham Gujare: sir , can you do one sum on mod x asynchronous down counter (x can be anything)
115. Keziah Rinny: well explained sir..all my doubts are cleared after watching this video.
116. Haseeb Sheikh: How to make 12 mod counter
117. Kranti Roy: when the 3 bit counter counts 7 (111)....the clear is not 0....then isn't it going to count 7
118. Badal Harplani: please upload for mod-6 down counter
119. Brian: why not just use Qb and Qc for the input of the NAND gate for clr? when Qb = 1 and Qc = 1 and inputed into a NAND gate the result will be 0? and this only happens at 110 and 111 so why do we even need to include Qa????
120. sunny jain: sir,first of all thanks for this video. my question is how to generate any series of no like 0,1,2,4,7....series how to jump more than a single no please help me!
121. Amit Englstein: What if I'd like to perform this way of counting: 0--> 3-->6-->2-->3-->5-->6? Will it be possible using the counting way u've shown us?
122. MCA Shadow: how if i want mod 7 but from 10 to 4
123. Ashwin Singh: anyone can explain mod-7 asynchronous counter
124. Mayur Naik: sir, I have a doubt while making mod 6 counter cant we just use Qc nand Qb because when both are 1 we shud reset it so cant we just use this instead of 3 input nand gate?
125. LORD SHIVA: u have to use extra combinational cktry for preset clear. first made state diagram and then you will know wht to do by yourself
126. Sahil Pathak: You guys are doing a great job.
127. Kunal Hirani: Very Clear Explanation amazing! Worth Watching ads! :)
128. Mrunank Mistry: really useful video!!!!!!!!!!!!
129. KRISHNA SIMHA VEMULAPALLI: if we do what u have said...5th count state will be unstable...so when 6 came it is cleared..and 000 will come
130. Arihant Jain: keep posting such videos..!!!! very helpful...!!!!
131. SHUBHAM YADAV: Design ripple counter count from MOD 3 to MOD 13
132. amarnath chitrakunta: How to start count from a particular value!
133. Aditya Aswal: The inputs of the AND gates should be Qa , Qb and Qc as binary representation of 7 is 111(QaQbQc)
134. red cat: How to make a mod 6 synchronized counter?
135. gaurav gill: PST should be equal to 1 @9:49 both 0 are not used i guess
136. ajay jadhav: counting starts after 1st clock pulse suggesting that actual counting starts from 1
137. Nehal Chavan: one request i want to do is, post videos on VHDL and memories as soon as possible.
138. Kesineni Sireesha: These videos are very useful to me. U'r way of teaching style is excellent. Very thankful sir......
139. khanjan gajera: Excellent teaching .
140. Manoj Guha: Thank you very much .. Clear and precise explanation better than any book
141. Ram Aditya: sir , why have you used a NOT gate infront Qa?
142. phan thanh thư: Great! Now I got it. Thank you so much.
143. Gergő Tanyi: I couldn't get to understand counters up till now. Thank you very much. I keep studying from you videos.
144. Neel Chaudhary: Mr. this is counters, not a binary showing machine.It's count from either 0 or 7.
145. subhashree shivani: Almost like classroom teaching.. very nice... Appreciate all the effort :)
146. WBSISC MCH: how to make 2421 counter
147. Hisyam Muhamad: what happen if only two clear is connected to the nand gate, if the A FF is not connect to the nand gate
148. Rabia A: thank u soo much !!
149. Neso Academy: Because we want the complete fifth pulse.
150. Jaydeep Paul: Sir, can we just solve the K-Map for MOD 6 counter?? Then combinational logic will become NAND of Qb and Qc..
151. Bithi Dey dey: sir can you pls upload opamp!!!!
152. Shruti Deshpande: thanku sir! your lectures have helped me a lot😊
153. muhammad asad: assalam o alakum i just want to say you are the best teacher of this subject
154. prajareddy 888: How Will we design mod 10 counter
155. ravi sinha: IF we take case of qc=1,qb=1,qa=1....then clr becomes 1......then it may count,please make it clear sir
156. Himanshu Tyagi: sir plz explain the output frequeny in this type of counter(decade counter)...
157. faryz ryz: wow , works like charm , thanks
158. Swarna Bharathi: please can u explain a mod 6 ripple counter ,given that all the other unused states are 100
159. Abdullah Mushtaq: Sir i wanted to ask u that u have given preset as logic 1 in BCD ripple counter but u didn't give preset as logic 1 in MOD 6 counter why is that so???
160. Himamshu C: Thnk u very much sir
161. ajay arya: GOD give me gift through you. so thankyou so much sir. please upload remaining video as soon as possiable . i highly obliged for this
162. Sarthak Sengupta: 6 will be the output(QcQbQa) for the time equal to the propagation delay of the combinational circuit. As soon as the combinational circuit detects 6(110) as input, the clear is set to 0. This clear will ASYNCHRONOUSLY (ie . clock independently without encountering the negative edge)update the outputs as 000(QcQbQa) and the counter will function as normal for next states. *Clear and Preset are asynchronous overriding inputs. .They don't depend on the clock edge.
163. Shafly Hamzah: thank you!
164. Neso Academy: +Revanth Raj Hello!! I will upload synch. counters before Sunday.
165. Umesh: very nice lecture keep up loading such nice lecture..
166. Kevin Zhao: +Sarthak Sengupta thx
167. Neso Academy: +Trai Welcome!
168. Neso Academy: Welcome!
169. Arun Singh: why reset is done when value is 6 why not a 5 ..
170. deberjeet usham: Can someone tell me how to count from 2 to 6, not 0 to 6
171. SWATI GUTTEDAR: Clear signal being asynchronous, don't you think it Shud obey removal and recovery time?
172. Tayyab Tahir: fabulous brother, you are great teacher..........................................
173. Maddula Abhijit: very clear and helpful. A big thanks from RV college of engineering student.
174. Shah Rahul: Sir jab count 7 hoga tab ? nand gate wont click on clear as its o/p is 0 only for 6 not for 7
175. Hoang Tran: What if i want a synchronous divide by n counter ?
176. sam: but when we see the excitation table of flip flop when we are giving J K Qn Qn+1 1 1 dont care 1 so why we are taking input Q as 1 always and why if we preset = 0 then QA will always be 1?
177. Shyam Rathod: how to design mod11 counter using jk flipflop
178. Meghna SIngh: Whenever it hits 110, counter output is going to be RESET, so 111 state never achieved and all states start back from 000.
179. Karthik M: You are the best...;)
180. balram sharma: thank u wo much neso academy
181. Hitarth Patel: Can you do a video on how to design a synchronous mod 10 up counter?
182. GOD-se Sahil: really it was helpful for me during exam period.
183. Ahmad Sayeb: thanx allot...but i have a question....i created the Karno map for the clear and i have found that we can say CL= QB'+QC' ... can we use that as the clear input??
184. Kodipalli Vaishnavi: why can't we use any other gate other than nand for clear??
185. Sammy Mwangi: great ideology....
186. Shiva Sharma: sir your greatest teacher I ever know. Pleeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeease sir ,upload classes for Artificial Intelligence, Neural Network, Graphics in computer science.
187. Sagar Bhatia: How to design mod 10 synchronous counter
188. Amogha Subramanya D A: Since, the clear input is active low, we have to use NAND gate for 7476 JK Flip-flop IC to Reset.
189. Song4 U: Sir what about 111
190. Sahil Pathak: You guys are doing a great job.
191. anuthomas kallely: Sir please tell about MOD 10 counter
192. Samuel Caetano: Why does it need to be a NAND gate? I didnt get it...
193. Hassan Alshehri: +Neso Academy Oh, I see. Thank you for clarifying this to me.
194. kamlesh kunwar: tutorial has a bug .. for mod 7 urs input should b 110(6)
195. Anmol: sir..modulus is applicable only on asynchronous counters...or it an be applied on synchronous counter as well??
196. boga rakesh: one more examples
197. Abbas Sadiq: u don't have any video on presettable counters? if there plz share the link
198. Srinivas Polavarapu: how do i design a mod 15 counter

Modulus of the Counter & Counting up to Particular Value
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Education	Upload TimePublished on 30 Mar 2015